At least one interleaving step, for example data block reordering according to a specific permutation, is required in many telecommunications protocols and hence there has been a trend such that an interleaving step is to be found in virtually every radio processing chain.
Another more recent trend is to provide telecommunications devices such as mobile phones that are adapted to use various standards. Processing of received signals is typically standard specific and hence there are demands on the interleaving architectures of a telecommunication device for it to be adapted to different standards or to be re-configurable to one or more different standards.
The ever increasing throughput demands for interleaving architectures typically lead to multi-bank memory solutions. In order to address multiple memory banks simultaneously, a vector processor is preferably incorporated as a vector address generator. Ideally, a full vector of P addresses is produced by this vector address generator every clock cycle, when there are P data elements stored in memory. Because of their characteristics, not all required address sequences allow for on-the-fly generation of P addresses at every clock cycle. This leads to a lower address vector rate and thus a lower multi-bank memory usage efficiency.
Known solutions for interleaving can be categorized as follows:                Low-rate interleaving on microcontrollers or DSPs                    Addresses are generated sequentially and in general the efficiency of address generation is very low.                        High-rate interleaving on dedicated HW (hardware)                    Dedicated HW solutions have limited or no reconfigurability and are therefore not suitable for multi-standard interleaving.                        A related situation relates to high throughput interleaving in Turbo Decoders. Multi-bank interleaving solutions are available for this application, but are standard specific (i.e. they are not reconfigurable).        
High throughput requirements on interleavers have the following consequences:                Data input and output, to and from the interleaver, typically needs to be done in parallel (i.e. multiple data elements at a time: data vectors)        Processing P data elements simultaneously requires P addresses to be available each clock cycle.        
Look-up table solutions can provide P addresses each clock cycle, but the number of required tables grows enormously when the number of standards to be supported rises.
In the general case of multi-standard address generation, the goal of generating P addresses every clock cycle can typically be realized only partially. As a result there is less than P addresses per clock cycle. This leads to “partial address vectors”, which are vectors that are not completely filled but contain less than P valid addresses.